In an active matrix liquid crystal display device adopting TFTs as selection elements of respective picture elements, it is well known that a feed through phenomenon occurs (See Non-Patent Document 1, for example). The following briefly explains such a feed through phenomenon.
FIG. 8 is an equivalent circuit of one picture element. One picture element PIX is provided so as to correspond to an intersection of a gate bus line GL and a source bus line SL. The picture element PIX includes a TFT 101, a liquid crystal capacitance Clc, and a storage capacitance Cs. In addition, the picture PIX, in general, includes a parasitic capacitance such as a capacitance Cgd or the like formed between a picture element electrode 102 and the gate bus line GL. A gate of the TFT 101 is connected to the gate bus line GL; a source of the TFT 101 is connected to the source bus line SL; and a drain of the TFT 101 is connected to the picture element electrode 102. The liquid crystal capacitance Clc is formed in a configuration in which a liquid crystal layer is provided between the picture element electrode 102 and a common electrode to which a voltage Vcom is applied. The storage capacitance Cs is formed in a configuration in which a dielectric layer is provided between (i) a storage capacitance bus line to which a voltage Vcs is applied and (ii) the picture element electrode 102 or an electrode that is connected to the picture element electrode 102. The voltage Vcs is equal to, for example, the voltage Vcom, but may also be a voltage of other value.
As shown in FIG. 9, to the gate bus line GL, a selection signal Vg is outputted from a gate driver. The selection signal Vg includes two value levels that include a gate high voltage Vgh and a gate low voltage Vgl. A gate pulse of the selection signal Vg has a peak-to-peak voltage expressed by Vgp-p=Vgh−Vgl. Further, to the source bus line SL, a positive-polarity data signal (hereinafter, referred to as a positive data signal) Vsp and a negative-polarity data signal (hereinafter, referred to as a negative data signal) Vsn are outputted from a source driver while these signals are switched to each other by AC drive.
FIG. 9 focuses on one picture element PIX and shows a state in which a positive data signal Vsp is written, as a data signal Vs, to the picture element electrode 102 in one frame period TF1, and in a next frame period TF2, a negative data signal Vsn is written to the picture element 102.
Prior to the frame period TF1, a potential Vdn has been written to the picture element electrode 102. In the frame period TF1, the gate pulse of the selection signal Vg is applied to the gate of the TFT 101 and the TFT 101 is turned ON. Then, a potential is written toward the Vsp of the data signal Vsp to the picture element electrode 102. As a result, the liquid crystal capacitance Clc and the storage capacitance Cs are charged. Then, when the gate pulse falls, the TFT 101 is turned OFF and the writing to the picture element electrode 102 ends. At this time, the gate pulse has an abrupt change from the gate high voltage Vgh to the gate low voltage Vgl. Accordingly, due to the feed through phenomenon via the capacitance Cgd that is the parasitic capacitance between the picture element electrode 102 and the gate bus line GL, a potential of the picture element electrode 102 decreases by a voltage ΔVd and a potential of the picture element electrode 102 becomes Vdp that is lower than a potential of the data signal Vsp. This voltage ΔVd is called a feed through voltage. The voltage ΔVd is expressed as follows:
                                                                        Δ                ⁢                                                                  ⁢                Vd                            =                                                                    (                                          Cgd                      /                      Cpix                                        )                                    ·                  Vgp                                -                p                                                                                                        =                                                      (                                          Cgd                      /                      Cpix                                        )                                    ·                                      (                                          Vgh                      -                      Vgl                                        )                                                              ,                                                          (        1        )            where Cpix is a total capacitance of a picture element that is a sum of the liquid crystal capacitance Clc, the storage capacitance Cs, and the parasitic capacitance such as the capacitance Cgd or the like. In a case where only the capacitance Cgd is taken into consideration as a parasitic capacitance in FIG. 8, Cpix=Clc+Cs+Cgd.
Prior to the frame period TF2, a potential Vdp has been written to the picture element electrode 102. In the frame period TF2, the gate pulse of the selection signal Vg is applied to the gate of the TFT 101 and the TFT 101 is turned ON. Then, a potential is written toward the potential Vsn of the data signal Vsn to the picture element electrode 102. As a result, the liquid crystal capacitance Clc and the storage capacitance Cs are charged. Then, as in the frame period TF1, when the gate pulse falls, a potential of the picture element electrode 102 decreases by a voltage ΔVd due to the feed through phenomenon via the capacitance Cgd and a potential of the picture element electrode 102 becomes Vdn that is lower than a potential of the data signal Vsn.
In the liquid crystal display panel, due to the occurrence of this feed through phenomenon, in a case where the voltage Vcom is set to the center of a voltage range between a voltage range of the positive data signal Vsp and a voltage range of the negative data signal Vsn, the voltage Vcom becomes a value that is shifted to a higher value by ΔVd from the center value of a voltage range between a positive range and a negative range of the voltages held after writing to the picture element electrode 102. Accordingly, in each picture element PIX, positive-polarity and negative-polarity voltages across the liquid crystal layer have different effective values. This causes deterioration in display quality and deterioration in liquid crystals.
In order to solve this problem, it is possible to take a method according to which, by correcting gray scale data to be supplied to the source driver by a change amount of ΔVd in advance, an influence of the feed through phenomenon is compensated. That is, a voltage of the data signal supplied to the picture element PIX decreases by ΔVd after completion of writing to the picture element electrode 102. This means that, substantially, the source driver supplies, to the picture element PIX, data signal that is lower by ΔVd than a target value. Therefore, the gray scale data to be supplied to a display controller is corrected to gray scale data corresponding to a data signal whose voltage is shifted so as to be increased by the voltage ΔVd. Then, thus corrected gray scale data is supplied to the source driver.
However, on the display panel, the gate bus line GL has a resistance component and a capacitance component as distributed constants. Accordingly, the gate pulse outputted from the gate driver to the gate bus line GL reaches, with a propagation delay, the gate of the TFT 101 of each picture element PIX. As a result, a waveform of the gate pulse receives a greater influence of the delay at a position farther from a position at which the gate driver outputs the gate pulse. For example, as shown in FIG. 10, in a case where a gate pulse VG(j) of the j-th gate bus line GL is generated by the gate driver and a waveform of this gate pulse VG (j) is an ideal square pulse, a delay of a gate pulse Vg (1, j) that reaches a picture element PIX of a first column of the j-th line is small whereas a delay of a gate pulse Vg (N, j) that reaches a picture element PIX of an Nth column of the j-th line is large.
A threshold voltage VT of the TFT 101 is present as a potential at some midpoint in a fall of the gate pulse. Accordingly, if the gate pulse falls slowly due to the delay, a smaller change amount SyN per time unit in the fall of the gate pulse shown in FIG. 10 results in a longer transition time that the TFT 101 takes for transition to an OFF state. In addition, in such a case, a waveform of the gate pulse has a gentler slope, before the gate pulse decays to a gate low level after the TFT 101 is turned OFF. As a result, a feed through regarding the capacitance Cgd becomes smaller. This makes ΔVd smaller. This is inconsistent with the expression (1) that can be derived from an electrostatic solution that employs only the law of conservation of charge.
In other words, a change amount SyN is smaller when a distance from a position of the output of the gate driver to the gate is larger. Accordingly, the voltage ΔVd has a distribution such that the voltage ΔVd is smaller in a picture element PIX that has a larger distance from the position of the output of the gate driver on the display panel. In FIG. 10, in a picture element PIX to which a gate pulse Vg (1, j) with a small delay is applied, a potential of the picture element electrode 102 abruptly changes and a decrease of ΔVd(1) in potential occurs. Meanwhile, in a picture element PIX to which a gate pulse Vg (N, j) with a large delay is applied, a potential of the picture element electrode 102 slowly changes and a decrease of ΔVd(N) in potential occurs. Here, ΔVd(1)>ΔVd(N).
For the above reason, in a case where all gray scale data that is to be supplied to the source driver is uniformly corrected, a feed through phenomenon cannot be cancelled out uniformly within a plane of the panel. As a result, unevenness in display quality occurs.
In order to solve this problem, for compensating the feed through phenomenon by correcting the gray scale data, a certain distribution in correction amount of the gray scale data is provided within the plane of the panel.
For example, in the display panel as shown in (a) of FIG. 11, the gate pulse is supplied to each gate bus line from both sides of the panel. Accordingly, in a case where a position on the display panel is expressed by using a position of a column, the closer to a column at an end section A of the panel a picture element PIX is, the larger a voltage ΔVd of this picture element PIX becomes. Meanwhile, in such a case, the closer to a column at a center section C of the panel a picture element PIX is, the smaller a voltage ΔVd of this picture element PIX becomes. Accordingly, as shown in (b) of FIG. 11, in a case where a positive data signal Vsp or negative data signal Vsn corresponding to certain gray scale data is uniformly set as indicated by a dotted line within the plane of the panel (i.e., in a left-right direction of the panel), both a positive picture element electrode potential Vdp and a negative picture electrode potential Vdn of a picture element electrode potential Vd after the occurrence of the feed through phenomenon shows a distribution in a curved form, as shown by a solid line, which is convex upward and has a top at the column at the center section C of the panel. In this case, the voltage across the liquid crystal layer in accordance with positive gray scale data is the largest at the center section C of the panel and gradually decreases towards end sections A of the panel from the center section C through intermediate sections B of the panel. Meanwhile, the voltage across the liquid crystal layer in accordance with negative gray scale data is the smallest at the center section C and gradually increases towards the end sections A from the center section C through the intermediate sections B of the panel. Accordingly, as indicated by the dotted line in (c) of FIG. 11, gray scale data of picture elements are corrected so that, before the gray scale data is supplied to the display driver, the distribution of the voltage ΔVd is compensated in advance, that is, the gray scale data has a distribution in which data signal voltages Vdp and Vdn are higher at positions closer to the end sections A of the panel. This makes the picture element electrode potentials Vdp and Vdn after the occurrence of the feed through phenomenon be uniform, as indicated by the solid line, within the panel plane.
In the correction of the gray scale data, now, a case where gray scale levels closer to a normally black or white level are set to be on a lower gray scale level side is considered. In this case, as show in FIG. 12, positive input gray scale data is corrected so that: a value of gray scale data to be supplied to a picture element PIX at the center section C of the panel is increased only by a small number of gray scale levels; and a value of gray scale data is increased by a larger number of gray scale levels as a position of a picture element PIX to which the gray scale data is supplied approaches either of the end sections A from the center section C of the panel. Meanwhile, negative input gray scale data is corrected so that: a value of gray scale data to be supplied to a picture element PIX at the center section C of the panel is decreased only by a small number of gray scale levels; and a value of gray scale data is decreased by a larger number of gray scale levels as a position of a picture element PIX to which the gray scale data is supplied approaches either of the end sections A from the center section C of the panel.
In this way, in a case where the gray scale data is corrected so that the in-plane distribution of the voltage ΔVd is compensated, potentials are written to the picture elements PIX in accordance with data signals corresponding to corrected gray scale data. Therefore, even in a case where a potential of the picture element electrode 102 decreases by the voltage ΔVd after the writing, it is possible to make the positive data signal and the negative data signal uniformly have effective values equal to each other in a plane while the common electrode potential Vcom is not changed.